Semiconductor device and methods of manufacturing the same

ABSTRACT

A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 12/465,013, filed on May 13, 2009, which claims the benefit ofKorean patent application number 10-2008-0052740, filed on Jun. 4, 2008,in the Korean Intellectual Property Office, the contents of whichapplications are incorporated herein in their entirety by reference.

BACKGROUND

The present invention disclosed herein relates to semiconductor devicesthat prevent misalignment of interconnections disposed at a smallinterval and a plug, and methods of manufacturing the same.

Semiconductor devices may be formed to include a plurality of layerssuch that a plurality of unit devices may be integrated in asemiconductor device. Interconnections may be disposed in a plurality oflayers and may be electrically connected to one another. A vertical plugmay be formed between layers to electrically connect interconnections.An alignment process is important in order to accurately contactinterconnections with the plug connected to the interconnections.

Moreover, as demand for high-integration semiconductor devicesincreases, space between patterns or interconnections of a semiconductordevice is becoming rapidly reduced. As a result, alignment margin isreduced. If misalignment occurs when interconnections formed ondifferent layers are connected to one another, interconnections thatmust not be connected may be connected. Since the misalignment may causea malfunction, reliability of a device may be degraded.

SUMMARY

Exemplary embodiments provide a method of manufacturing a semiconductordevice. The method may include forming plugs in an interlayer insulatinglayer on a substrate, forming a protection layer on the interlayerinsulating layer and the plugs, forming molding patterns overlapped withedges of the plugs on the protection layer, forming a mask pattern onthe protection layer and the molding patterns, the mask pattern exposingthe protection layer on the plugs, forming a protection pattern exposingthe plugs by removing the exposed protection layer using the maskpattern and the molding patterns as an etching mask, removing the maskpattern and forming interconnections between the molding patterns, theinterconnections being electrically connected to the plugs.

In one embodiment, the method further comprises stacking hard maskpatterns on the molding patterns. In one embodiment, the protectionlayer includes a material having an etching selectivity with respect tothe mask pattern and the hard mask patterns. In one embodiment, formingthe molding patterns and the hard mask patterns comprises: forming amolding layer on the protection layer; forming a polysilicon layer onthe molding layer; forming a photoresist pattern on the polysiliconlayer; continuously etching the polysilicon layer and the molding layerusing the photoresist pattern; and removing the photoresist pattern. Inone embodiment, the method further comprises, after removing the maskpattern, removing the polysilicon layer. In one embodiment, forming themolding patterns and the hard mask patterns is performed by a doublepatterning technique.

In one embodiment, the plugs are formed in a zigzag pattern. In oneembodiment, forming the plugs comprises: forming first plug holes andsecond plug holes which are exposing the substrate by selectivelyetching the interlayer insulating layer; and filling the first plugholes and the second plug holes with conductive material. The first plugholes and the second plug holes can be disposed along a first direction,and each of the second plug holes can be disposed between adjacent firstplug holes and is spaced apart from first plug holes toward a seconddirection crossing the first direction.

In one embodiment, the mask pattern includes openings having the samewidth and arrangement as the plugs. In one embodiment, forming the maskpattern comprises: forming a spin-on hard mask layer on the protectionlayer and the hard mask pattern so as to fill a space between themolding patterns; forming a photoresist layer on the spin-on hard masklayer; selectively exposing the photoresist layer; selectively removingthe photoresist layer on the plugs; and removing the spin-on hard masklayer exposed by a removal of the photoresist layer.

In one embodiment, the protection layer includes silicon nitride, themolding patterns include silicon oxide, the hard mask patterns includepolysilicon and the mask pattern includes photoresist.

In one embodiment, the method further comprises forming a stringselection line which is adjacent to the plugs on the substrate andextends in the first direction, word lines adjacent to the stringselection line and a ground selection line adjacent to the word lines.

Exemplary embodiments provide a semiconductor device. The semiconductordevice may include an interlayer insulating layer on a substrate; plugsdisposed in the interlayer insulating layer in a first direction;interconnections which extend in a second direction perpendicular to thefirst direction, and include a connection portion which has a widthsmaller than a width of the first direction of the plugs and is incontact with the plugs, the interconnections having the same width asthe connection portion in the first direction; and a protection patternin which the connection portion penetrates, the protection pattern beinginterposed between the interlayer insulating layer and theinterconnections and extending on the interlayer insulating layer andthe plugs.

In one embodiment, the plugs include first plugs and second plugs. Thefirst plugs and the second plugs are disposed in the first direction,and each of the second plugs is disposed between the adjacent firstplugs and is spaced apart from the first plugs in the second direction.

In one embodiment, the connection portion has same width as top surfacesof the plugs in the second direction.

In one embodiment, the device further comprises molding patterns betweenthe interconnections.

In one embodiment, the molding patterns which are in contact with sidesurfaces of the interconnections extend in the second direction and areoverlapped with edges of the plugs to be disposed on the protectionpattern. In one embodiment, the molding patterns include material havingan etching selectivity with respect to the protection layer.

In one embodiment, the protection pattern includes silicon nitride andthe molding patterns include silicon oxide.

In one embodiment, the device further comprises a string selection linewhich is adjacent to the plugs on the substrate and extends in the firstdirection, word lines adjacent to the string selection line and a groundselection line adjacent to the word lines.

BRIEF DESCRIPTION OF THE FIGURES

The foregoing and other features and advantages of the invention will beapparent from the more particular description of preferred embodimentsof the invention, as illustrated in the accompanying drawings in whichlike reference characters refer to the same parts throughout thedifferent views. The drawings are not necessarily to scale, emphasisinstead being placed upon illustrating the principles of the invention.In the drawings, the thickness of layers and regions are exaggerated forclarity.

FIG. 1 is a top plan view of a semiconductor device according to anembodiment of the present invention.

FIG. 2 is a cross sectional view taken along the lines I-I′ and II-II′of FIG. 1 illustrating a semiconductor device according to an embodimentof the present invention.

FIGS. 3, 5, 7, 9 and 11 are top plan views illustrating a method ofmanufacturing a semiconductor device according to an embodiment of thepresent invention.

FIGS. 4, 6, 8, 10 and 12 are cross sectional views taken along the linesI-I′ and II-II′ of FIGS. 3, 5, 7, 9 and 11, respectively, illustrating amethod of manufacturing a semiconductor device according to anembodiment of the present invention.

FIGS. 13, 15, 17 and 19 are top plan views illustrating another methodof manufacturing a semiconductor device according to an embodiment ofthe present invention.

FIGS. 14, 16, 18 and 20 are cross sectional views taken along the linesI-I′ and II-II′ of FIGS. 13, 15, 17 and 19, respectively, illustratinganother method of manufacturing a semiconductor device according to anembodiment of the present invention.

FIG. 21 is a top plan view of a semiconductor device according toanother embodiment of the present invention.

FIG. 22 is a cross sectional view taken along the lines I-I′ and II-II′of FIG. 21 illustrating a semiconductor device according to anotherembodiment of the present invention.

FIGS. 23, 25, 27 and 29 are top plan views illustrating a method ofmanufacturing a semiconductor device according to another embodiment ofthe present invention.

FIGS. 24, 26, 28 and 30 are cross sectional views taken along the linesI-I′ and II-II′ of FIGS. 23, 25, 27 and 29, respectively, illustrating asemiconductor device according to another embodiment of the presentinvention.

FIG. 31 is a block diagram illustrating an electronic device including asemiconductor device according to embodiments of the present invention.

FIG. 32 is a block diagram illustrating a memory system including asemiconductor device according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this description will be thorough and complete, and will fullyconvey the invention to those skilled in the art. In the drawings, thesize and relative sizes of layers and regions may be exaggerated forclarity.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed itemsand may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first region/layer could be termeda second region/layer, and, similarly, a second region/layer could betermed a first region/layer without departing from the teachings of thedisclosure.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” or “includes” and/or “including” when used in thisspecification, specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Embodiments of the present invention may be described with reference tocross-sectional illustrations, which are schematic illustrations ofidealized embodiments of the present invention. As such, variations fromthe shapes of the illustrations, as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments of the present invention should not be construed as limitedto the particular shapes of regions illustrated herein, but are toinclude deviations in shapes that result from, e.g., manufacturing. Forexample, a region illustrated as a rectangle may have rounded or curvedfeatures. Thus, the regions illustrated in the figures are schematic innature and are not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present application, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

In the drawings, the thickness of layers and regions are exaggerated forclarity. It will also be understood that when an element such as alayer, region or substrate is referred to as being “on” or “onto”another element, it may lie directly on the other element or interveningelements or layers may also be present. Like reference numerals refer tolike elements throughout the specification.

Spatially relatively terms, such as “beneath,” “below,” “above,”“upper,” “top,” “bottom” and the like, may be used to describe anelement and/or feature's relationship to another element(s) and/orfeature(s) as, for example, illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use and/or operation in additionto the orientation depicted in the figures. For example, when the devicein the figures is turned over, elements described as below and/orbeneath other elements or features would then be oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly. As used herein, “height” refers toa direction that is generally orthogonal to the faces of a substrate.

Referring to FIGS. 1 and 2, a semiconductor device according to anembodiment of the present invention will be described.

Plugs 130 in contact with a substrate 110 may be disposed in aninterlayer insulating layer 120. The plugs 130 may include first plugs130 a and second plugs 130 b. The plugs 130 may be disposed in astaggered or “zigzag” pattern as shown. The plugs 130 may be spaced afirst distance (D1) apart from each other to extend in a first direction(A1). The first distance (D1) may be a minimum distance that can beobtained by a photolithography process. Alternatively, the firstdistance (D1) may be greater than the minimum distance. A first width(W1) of the plugs 130 may be greater than a minimum width that can beobtained by a photolithography process.

Only the first plugs 130 a may be adjacent to one another in the firstdirection (A1). The second plugs 130 b may be arranged to be adjacent toone another in the first direction (A1). Each of the second plugs 130 bmay be disposed between the first plugs 130 a adjacent to one another inthe first direction (A1), and is spaced apart from the first plugs 130 ain a second direction (A2) perpendicular to the first direction (A1).The first plugs 130 a and the second plugs 130 b may be disposed at asufficiently wide interval so as not to be overlapped with one another.

A protection pattern 145 including a protection pattern opening 142 maybe disposed on the plugs 130 and the interlayer insulating layer 120. Abottom surface of the protection pattern opening 142 may be constitutedof a portion of a top surface of the plug 130. The protection patternopening 142 may have a minimum width or less that can be obtained by aphotolithography process in the first direction (A1). The protectionpattern opening 142 may have a width the same as a width of the plugs130 in the second direction (A2). A width of the protection patternopening 142 may be wider in the second direction (A2) than in the firstdirection (A1). An edge of a top surface of the plug 130 may beoverlapped with the protection pattern 145 in the first direction (A1).

Molding patterns 155 may be disposed on the protection pattern 145 inthe second direction (A2). The molding pattern 155 may have a line shapeand the protection pattern opening 142 may be disposed between themolding patterns 155. A distance between the molding patterns 155 may beequal to a width of the first direction (A1) of the protection patternopening 142. A side surface of the molding pattern 155 and a sidesurface of the protection pattern opening 142 may be aligned with thesame side surface. The molding pattern 155 may be overlapped with anedge of a top surface of the plug 130 in the first direction (A1). Themolding pattern 155 may be disposed at a minimum interval that can beobtained by a photolithography process. The protection pattern 145 mayinclude a silicon nitride and the molding pattern 155 may include asilicon oxide.

Interconnections 195 may be disposed between the molding patterns 155.The interconnections 195 may include a connection portion 192 fillingthe protection pattern opening 142. The connection portion 192 may havethe same width as the interconnections 195 in the first direction (A1)and may have the same width as the plugs 130 (e.g., a top surface of theplug) in the second direction (A2). The plugs 130 may be electricallyconnected to the interconnections 195 by the connection portion 192. Theinterconnections 195 may include a conductive material, in oneembodiment a metal material. The metal material has a low resistance anda low ion migration in the interconnections. The metal material mayinclude aluminum, aluminum alloy or copper. A barrier layer (not shown)may be interposed between the interconnections 195 and the moldingpatterns 155, between the interconnections 195 and the protectionpattern 145, and between the interconnections 195 and the plugs 130. Thebarrier layer can improve a contact characteristic and can prevent adiffusion of metal ions and impurities.

Referring to FIGS. 1 through 12, a method of manufacturing asemiconductor device according to an embodiment of the present inventionwill be described.

Referring to FIGS. 3 and 4, a substrate 110 may be provided. Thesubstrate 110 is a semiconductor, for example a silicon wafer. Thesubstrate 110 may be a silicon oxide insulator (SOI). An interlayerinsulating layer 120 may be formed on the substrate 110. Plug holes 122exposing a portion of the substrate 110 may be formed in the interlayerinsulating layer 120. The plug holes 122 may include first plug holes122 a and second plug holes 122 b, and may be formed in the staggered orzigzag configuration. The plug holes 122 may be disposed to be spaced afirst distance (D1) apart from one another in a first direction (A1).The first distance (D1) may be a minimum distance that can be obtainedby a photolithography process. The first distance (D1) may be greaterthan the minimum distance. A first width (W1) of the plug holes 122 maybe greater than a minimum width that can be obtained by aphotolithography process.

Only the first plug holes 122 a may be adjacent to one another in thefirst direction (A1). At this time, the second plug holes 122 b may bedisposed in the first direction (A1), but each of the second plug holes122 b may be disposed between the first plug holes 122 a adjacent to oneanother in the first direction (A1) and is spaced apart from the firstplug holes 122 a in a second direction (A2) perpendicular to the firstdirection (A1). The first and second plug holes 122 a and 122 b may bedisposed at a sufficiently wide interval so as not to be overlapped withone another.

Plugs 130 filling the plug holes 122 with conductive material may beformed. The plugs 130 may include first plugs 130 a filling the firstplug holes 122 a and second plugs 130 b filling the second plug holes122 b. The plugs 130 may be formed by performing a step of forming aconductive layer and a step of planarizing the conductive layer.

Referring to FIGS. 5 and 6, a protection layer 140 may be formed on theplugs 130 and the interlayer insulating layer 120. A molding layer (notshown) may be formed on the protection layer 140 and hard mask patterns158 may be formed on the molding layer. The hard mask patterns 158 maybe formed by a photolithography process and an etching process. Themolding layer is etched using the hard mask patterns 158 to form themolding patterns 155. The molding patterns 155 may extend in the seconddirection (A2). The molding patterns 155 may have a line shape and maybe disposed at a minimum interval that can be obtained by aphotolithography process. The molding patterns 155 expose the protectionlayer 140 on the plugs 130 and may be overlapped with an edge of theplugs 130. The molding patterns 155 may include a material having anetching selectivity with respect to the protection layer 140. Forexample, the protection layer 140 may include a silicon nitride and themolding patterns 155 may include a silicon oxide.

Referring to FIGS. 7 and 8, a mask layer (not shown) may be formed onthe protection layer 140 and the hard mask patterns 158 so as to fill aspace between the molding patterns 155. The mask layer may include aphotoresist. The mask layer may include a spin-on hard mask materiallayer and a photoresist layer that are sequentially stacked. After aspace between the molding patterns 155 is first filled with a spin-onhard mask material having a superior gap-fill characteristic, thephotoresist layer may be formed. A reflection preventing layer may beinterposed between the spin-on hard mask material layer and thephotoresist layer so as to improve an efficiency of an exposure process.

A photolithography process may be applied to the photoresist layer. Aportion of the photoresist layer is selectively removed to form aphotoresist pattern and the spin-on hard mask material layer exposed bythe photoresist pattern may be etched. As a result, a mask pattern 165including openings 162 may be formed. The openings 162 may selectivelyexpose the protection layer 140 on the plugs 130. The openings 162 mayexpose the hard mask patterns 158 being on the molding patterns 155 andoverlapped with the plugs 130. For example, the openings 162 may beformed using the exposure mask used in forming the plug holes 122. Inthis case, the openings 162 may be formed to have a shape, a size (e.g.a width) and an arrangement as the plug holes 122 or the plugs 130 a and130 b.

Referring to FIGS. 9 and 10, the protection layer 140 exposed by theopenings 162 may be selectively etched using the mask pattern 165 andthe hard mask pattern 158. The protection layer 140 may include amaterial having an etching selectivity with respect to the mask pattern165, the hard mask patterns 158 and the plugs 130. The protection layer140 is etched to form a protection pattern 145 exposing a top surface ofthe plugs 130.

Referring to FIGS. 11 and 12, the mask pattern 165 and the hard maskpattern 158 may be removed. The molding patterns 155 may be disposed onthe protection pattern 145. Protection pattern openings 142 of theprotection pattern 145 exposing a top surface of the plugs 130 may havethe same interval as the molding pattern 155 in the first direction (A1)and the same width as the plugs 130 in the second direction (A2). Theprotection pattern openings 142 may exist only between the moldingpatterns 155.

Referring to FIGS. 1, 2, 11 and 12 again, interconnections 195 may beformed between the molding patterns 155. The interconnections 195 mayinclude a connection portion 192 filling the protection pattern openings142. The interconnections 195 may include conductive material, forexample a metal material. The metal material has a low resistance, forexample may include aluminum, aluminum alloy or copper. The metalmaterial may have a low ion migration in the interconnections. Theinterconnections 195 may be formed by a deposition process and aplanarization process. A copper interconnection may be formed by acopper damascene process. A barrier layer (not shown) may be interposedbetween the interconnections 195 and the molding patterns 155, betweenthe interconnections 195 and the protection pattern 145 and between theinterconnections 195 and the plugs 130. The barrier layer can improve acontact characteristic and prevent a diffusion of a metal ion and animpurity.

Referring to FIGS. 1, 2, and 13 through 20, another method ofmanufacturing a semiconductor device according to the present inventionwill be described.

Referring to FIGS. 13 through 18, molding patterns 155 may be formed atan interval smaller than a minimum interval that can be obtained by aphotolithography process. The molding patterns 155 may be formed usinghard mask patterns 175 a and 175 b formed by a double patterningtechnique (DPT). The hard mask patterns 175 a and 175 b may be formed tohave a same width.

Referring to FIGS. 13 and 14 again, a protection layer 140 may be formedon a resultant structure of FIGS. 3 and 4. A molding layer 150 may beformed on the protection layer 140. First hard mask patterns 175 a maybe formed on the molding layer 150. The molding layer 150 may includematerial having an etching selectivity with respect to the first hardmask patterns 175 a. For example, the molding layer 150 may includesilicon oxide and the first hard mask patterns 175 a may includepolysilicon. The first hard mask patterns 175 a may extend in the seconddirection (A2). The first hard mask patterns 175 a may have a line shapeand may be disposed at an interval greater than a minimum interval thatcan be obtained by a photolithography process.

Referring to FIGS. 15 and 16, second hard mask patterns 175 b extendingin the second direction (A2) may be formed between the first hard maskpatterns 175 a. The second hard mask patterns 175 b may include the samematerial as the first hard mask patterns 175 a.

According to an embodiment, the molding layer 150 exposed by the firsthard mask patterns 175 a may be recessed. The molding layer 150 may berecessed as much as the distance between the hard mask patterns 175 aand 175 b. A spacer layer 180 may be conformally formed on the firsthard mask patterns 175 a and the recessed molding layer 150. The spacerlayer 180 may be formed to have a same thickness as the recessed depthof the molding layer 150. The spacer layer 180 may include the samematerial as the molding layer 150. A space having the same width as thewidth of the first hard mask patterns 175 a may be formed between thefirst hard mask patterns 175 a by the spacer layer 180. After the spaceis filled with polysilicon, it is recessed to form second hard maskpatterns 175 b having a top surface even with the first hard maskpattern 175 a. The second hard mask patterns 175 b may have a bottomsurface even with a bottom surface of the first hard mask patterns 175 aby the spacer layer 180.

Referring to FIGS. 17 and 18 again, the spacer layer 180 and the moldinglayer 150 are anisotropically etched using the hard mask patterns 175 aand 175 b to expose the protection layer 140. The molding patterns 155may be formed on the protection layer 140 by the anisotropical etching.As a result, structures including the molding patterns 155 and the hardmask patterns 175 a and 175 b that are sequentially stacked on theprotection layer 140 may be formed. The structures may expose theprotection layer 140 on the plugs 130 and may be overlapped with an edgeof the plugs 130. The protection layer 140 may include having an etchingselectivity with respect to the hard mask patterns 175 a and 175 b. Forexample, the protection layer 140 may include silicon nitride and thehard mask patterns 175 a and 175 b may include polysilicon.

Referring to FIGS. 19 and 20, a mask layer (not shown) may be formed onthe structures and the protection layer 140. The mask layer may includea photoresist. Alternatively, the mask layer may include a spin-on hardmask material layer and a photoresist layer that are sequentiallystacked. After a space between the structures is first filled with aspin-on hard mask material having a superior gap fill characteristic,the photoresist layer may be formed. A preventing reflection layer maybe interposed between the spin-on hard mask material layer and thephotoresist layer.

A photolithography process may be applied to the photoresist layer. Aportion of the photoresist layer is selectively removed to form aphotoresist pattern and the spin-on hard mask material layer exposed bythe photoresist pattern may be etched. As a result, a mask pattern 165having openings 162 may be formed. The openings 162 may selectivelyexpose the protection layer 140 on the plugs 130. The openings 162 mayexpose the structures overlapped with the plugs 130. The openings 162may be formed to have a shape, a size and a disposition equal to theplug holes 122 or the plugs 130 a and 130 b. For example, the openings162 may be formed using the exposure mask used in forming the plug holes122.

The protection layer 140 exposed by the openings 162 may be selectivelyetched using the mask pattern 165 and the hard mask pattern 175 a and175 b. The protection layer 140 may include a material having an etchingselectivity with respect to the mask pattern 165, the hard mask patterns175 a and 175 b, and the plugs 130. The protection layer 140 is etchedto form a protection pattern 145 exposing a top surface of the plugs130.

Referring to FIGS. 1, 2, 19 and 20 again, the mask pattern 165 may beremoved. The hard mask patterns 175 a and 175 b may also be removed. Asa result, the molding patterns 155 may be exposed. The molding patterns155 may be disposed on the protection pattern 145. Protection patternopenings 142 of the protection pattern 145 exposing a top surface of theplugs 130 may have the same interval as the molding pattern 155 in thefirst direction (A1) and the same width as the plugs 130 in the seconddirection (A2). The protection pattern openings 142 may exist onlybetween the molding patterns 155.

Interconnections 195 may be formed between the molding patterns 155. Theinterconnections 195 may include a connection portion 192 filling theprotection pattern openings 142. The interconnections 195 may includeconductive material, for example a metal material. The metal materialmay have a low resistance and a low ion migration in theinterconnections. The metal material may include aluminum, aluminumalloy or copper. The interconnections may be formed by a depositionprocess and a planarization process. A copper interconnection may beformed by a copper damascene process. A barrier layer (not shown) may beinterposed between the interconnections 195 and the molding patterns155, between the interconnections 195 and the protection pattern 145 andbetween the interconnections 195 and the plugs 130. The barrier layercan improve a contact characteristic and prevent a diffusion of a metalion and an impurity.

Referring to FIGS. 21 and 22, a semiconductor device according toanother embodiment of the present invention will be described.Hereinafter, the descriptions of common features already described abovewill be briefly discussed.

Plugs 230 which are in contact with a substrate 210 may be disposed inan interlayer insulating layer 220 on the substrate 210.

The substrate 210 may include active regions 218 defined by a deviceisolation layer 215. A string selection line (SSL), a ground selectionline (GSL) and word lines (WL) between the string selection line (SSL)and the ground selection line (GSL) may be disposed on the substrate210. The lines (SSL, GSL, WL) may extend in a first direction (A1) andthe active regions 218 may extend in a second direction (A2)perpendicular to the first direction (A1).

The word lines (WL) may include a gate insulating layer 233, a floatinggate 224, an inter-gate dielectric layer 225 and a control gate 226 thatare sequentially stacked. The selection lines (SSL, GSL) may include agate insulating layer 233, a first gate 227, a dielectric layer 228 anda second gate 229. The first gate 227 and the second gate 229 may beelectrically connected to each other by a butting plug.

Impurity regions 212 may be formed in the active regions 218 between thelines (GSL, SSL, WL). The impurity regions 212 may include source/drainregions, a diffusion region and a common source line.

Plugs 230 in contact with a substrate 210 may be disposed in aninterlayer insulating layer 220. The plugs 230 may include first plugs230 a and second plugs 230 b. The plugs 230 may be disposed in zigzags.The plugs 230 may be spaced a first distance (D1) apart from one anotherto extend in a first direction (A1). The first distance (D1) may be aminimum distance that can be obtained by a photolithography process. Thefirst distance (D1) may also be greater than the minimum distance. Atthis time, a first width (W1) of the plugs 230 may be greater than aminimum width that can be obtained by a photolithography process.

Only the first plugs 230 a may be adjacent to one another in the firstdirection (A1). At this time, the second plugs 230 b may be disposed inthe first direction (A1), but each of the second plug 230 b may bedisposed between the first plug 230 a adjacent to one another in thefirst direction (A1) and is spaced apart from the first plugs 230 a in asecond direction (A2) perpendicular to the first direction (A1). Thefirst and second plugs 230 a and 230 b may be disposed at a sufficientlywide interval so as not to be overlapped with one another.

A protection pattern 245 including a protection pattern opening 242 maybe disposed on the plugs 230 and the interlayer insulating layer 220. Abottom surface of the protection pattern opening 242 may be constitutedof a portion of a top surface of the plug 230. The protection patternopening 242 may have a minimum width or less, in the first direction(A1), that can be obtained by a photolithography process. The protectionpattern opening 242 may have the same width as the plugs 230 in thesecond direction (A2). A width of the protection pattern opening 242 maybe greater in the second direction (A2) than in the first direction(A1). An edge of a top surface of the plug 230 may be overlapped withthe protection pattern 245 in the first direction (A1). Accordingly, theprotection pattern 245 may cover the edge of the top surface of the plug230 in the first direction (A1) and the interlayer insulating layer 220.

Molding patterns 255 may be disposed on the protection pattern 245 inthe second direction (A2). The molding patterns 255 may be disposed withan interval that is the same with a width of the protection patternopening 242 in the first direction (A1) where the protection patternopening 242 may be disposed between the molding patterns 255. A sidesurface of the molding pattern 255 and a side surface of the protectionpattern opening 242 may be aligned with the same side surface. Themolding pattern 255 may be overlapped with an edge of a top surface ofthe plug 230 in the first direction (A1). The protection pattern 245 mayinclude a silicon nitride and the molding pattern 255 may include asilicon oxide.

Interconnections 295 may be disposed between the molding patterns 255.The interconnections 295 may include a connection portion 292electrically connected to the plugs 230 by filling the protectionpattern opening 242, respectively. The connection portion 292 may havethe same width as the interconnections 295 in the first direction (A1)and may have the same width as the plugs 230 (e.g., a top surface of theplug) in the second direction (A2). The metal material may have a lowresistance and a low ion migration in the interconnections. The metalmaterial may include aluminum, aluminum alloy or copper.

Referring to FIGS. 21 through 30, a method of manufacturing asemiconductor device according to another embodiment of the presentinvention will be described. Hereinafter, the descriptions of commonfeatures already described above will be briefly discussed.

Referring to FIGS. 23 and 24, a string selection line (SSL), a groundselection line (GSL) and word lines (WL) between the string selectionline (SSL) and the ground selection line (GSL) may be disposed on asubstrate 210 including a device isolation layer 215. The deviceisolation layer 215 may be formed by a shallow trench isolation (STI)process and active regions 218 may be defined by the device isolationlayer 215. The lines (SSL, GSL, WL) may extend in a first direction (A1)and the active regions 218 may extend in a second direction (A2)crossing the first direction (A1).

The word lines (WL) may include a gate insulating layer 223, a floatinggate 224, an inter-gate dielectric layer 255 and a control gate 226 thatare sequentially stacked. The gate insulating layer 223 may be formed bya thermal oxidation process. A conductive pattern (not shown) extendingin the second direction (A2) may be formed. After forming an inter-gatedielectric layer and a conductive layer on the resultant structure, theword lines (WL) may be formed by patterning them. The selection lines(SSL, GSL) may include a gate insulating layer 223, a first gate 227, adielectric layer 228 and a second gate 229. The first gate 227, thedielectric layer 228 and the second gate 229 may be formed when thefloating gate 224, the inter-gate dielectric layer 225 and the controlgate 226 are formed, simultaneously. The first gate 227 and the secondgate 229 may be electrically connected to each other by a buttingprocess.

Referring to FIGS. 25 and 26, impurity regions 212 may be formed in theactive regions 218 exposed by the lines (GSL, SSL, WL) through animpurity implantation process. The impurity regions 212 may includesource/drain regions, a diffusion region and a common source line.

An interlayer insulating layer 220 may be formed on the substrate 210.Plug holes 222 exposing a portion of the substrate 210 may be formed inan interlayer insulating layer 220. The plug holes 222 may include firstplug holes 222 a and second plug holes 222 b. The plug holes 222 may bedisposed in zigzags. The plug holes 222 may be spaced a first distance(D1) apart from one another and extend in a first direction (A1). Thefirst distance (D1) may be a minimum distance that can be obtained by aphotolithography process. The first distance (D1) may also be greaterthan the minimum distance. At this time, a first width (W1) of the plugholes 222 may be greater than a minimum width that can be obtained by aphotolithography process.

Only the first plug holes 222 a may be adjacent to one another in thefirst direction (A1). The second plug holes 222 b may be disposed in thefirst direction (A1), but each of the second plug holes 222 b may bedisposed between the first plug holes 222 a adjacent to one another inthe first direction (A1) and is spaced apart from the first plug holes222 a in a second direction (A2) perpendicular to the first direction(A1). The first and second plug holes 222 a and 222 b may be disposed ata sufficiently wide interval so as not to be overlapped with oneanother.

Plugs 230 may be formed by filling the plug holes 222 with a conductivematerial. The plugs 230 may include first plugs 230 a in the first plugholes 222 a and second plugs 230 b in the second plug holes 222 b. Theplugs 230 may be formed by performing a step of forming a conductivelayer and a step of planarizing the conductive layer.

Referring to FIGS. 27 and 28, a protection layer 240 may be formed onthe resultant structure. Molding patterns 255 may be formed on theprotection layer 240. The molding pattern 255 may be formed using hardmask patterns 275. After a molding layer (not shown) is formed on theprotection layer 240, the hard mask pattern 275 may be formed on themolding layer. The molding layer may include material having an etchingselectivity with respect to the hard mask patterns 275. For example, themolding layer may include silicon oxide and the hard mask patterns 275may include polysilicon. The molding layer is etched using the hard maskpatterns 275 to form structures including the molding patterns 255 andthe hard mask patterns 275 that are sequentially stacked on theprotection layer 240.

The hard mask patterns 275 may be formed by a photolithography process.The hard mask patterns 275 may be formed at a minimum interval that canbe obtained by a photolithography process. The hard mask patterns 275may also be formed by a double patterning technique (DPT). At this time,the hard mask patterns 275 may be formed at an interval smaller than aminimum interval that can be obtained by a photolithography process.

Referring to FIGS. 29 and 30, the above structures expose the protectionlayer 240 on the plugs 230 and may be overlapped with edges of the plugs230. The protection layer 240 may include material having an etchingselectivity with respect to the hard mask patterns 275. The protectionlayer 240 may include silicon nitride and the hard mask patterns 275 mayinclude polysilicon.

A mask layer (not shown) may be formed on the structures and theprotection layer 240. After a space between the structures is filledwith a spin on hard mask material having a superior gap-fillcharacteristic, a photoresist layer may be formed. A mask pattern 265including openings 262 may be formed by a photolithography process. Theopenings 262 may expose the protection layer 240 on the plugs 230 andthe structures (i.e. the molding pattern 255 and the hard mask patternssequentially stacked) overlapped with the plugs 230. The openings 262may be formed to have the same shape, size (e.g. a width) anddisposition as the plug holes 222 (or the plugs 230). The openings 262may be formed using an exposure mask used in a formation of the plugholes 222.

The protection layer 240 exposed by the openings 262 may be selectivelyetched using the mask pattern 265 and the hard mask patterns 275. Theprotection layer 240 may include material having an etching selectivitywith respect to the mask pattern 265, the hard mask patterns 275 and theplugs 230. As a result, a protection pattern 245 having protectionpattern openings 242 exposing top surfaces of the plugs 230 may beformed. The protection pattern openings 242 may have the same intervalas the molding patterns 255 in the first direction (A1) and may have thesame width as the plugs 230 in the second direction (A2). The protectionpattern openings 242 may exist only between the molding patterns 255.

Referring to FIGS. 21, 22, 29 and 30 again, the mask pattern 265 and thehard mask patterns 275 are removed to expose the molding patterns 255.Interconnections 295 may be formed by filling a space between themolding patterns 255 with conductive material. The interconnections 295may include a connecting portion 292 filling the protection patternopenings 242. The connection portion 292 may have the same width as theinterconnections 295 in the first direction (A1) and may have the samewidth as the plugs 230 (e.g., a top surface of the plug) in the seconddirection (A2). The connection portion 292 may electrically connect theplug 230 and the interconnection 295. The metal material may have a lowresistance and a low ion migration in the interconnections. The metalmaterial may include aluminum, aluminum alloy and/or copper. Theinterconnections 295 may be formed by a deposition process and aplanarization process. A copper interconnection may be formed by acopper damascene process.

Referring to FIG. 31, an electronic device 300 including a memory deviceaccording to embodiments of the present invention will be described. Theelectronic device 300 may be used in a wireless communication devicesuch as a PDA, a laptop computer, a portable computer, a web tablet, awireless phone, a cell phone and a digital music player, or a devicethat can transfer and/or receive information in a wireless environment.

The electronic device 300 may include a controller 310, an input/outputdevice 320 such as a keypad, a keyboard and a display, a memory 330, awireless interface 340 that are combined with each other through a bus350. Controller 310 may include a microprocessor, a digital signalprocessor, a microcontroller, or the like. The memory 330 may be used tostore an instruction executed by the controller 310. The memory 330 mayalso be used to store user data. The memory 330 may include a memorydevice according to embodiments of the present invention.

The electronic device 300 may use the wireless interface 340 so as totransfer data to a wireless communication network communicating with RFsignal or receive data from the network. The wireless interface 340 mayinclude an antenna, a wireless transceiver and so on.

The electronic device 300 according to embodiments of the presentinvention may be used in a communication interface protocol of a thirdgeneration communication system such as CDMA, GSM, NADC, E-TDMA, WCDMA,CDMA2000.

Referring to FIG. 32, a memory system including a memory deviceaccording to embodiments of the present invention will be described.

A memory system 400 may include a memory device 410 and a memorycontroller 420 to store huge amounts of data. The memory controller 420controls the memory device 410 to read data stored in the memory device410 or write data to the memory device 410 in response to a request ofread/write of a host 430. The memory controller 420 may constitute anaddress mapping table to map an address provided from the host 430 (amobile device or a computer system) into a physical address of thememory device 410.

The foregoing is illustrative of the present invention and is not to beconstrued as limiting thereof. Although a few embodiments of the presentinvention have been described, those skilled in the art will readilyappreciate that many modifications are possible in the embodimentswithout materially departing from the novel teachings and advantages ofthe present invention. Accordingly, all such modifications are intendedto be included within the scope of the present invention as defined inthe claims. Therefore, it is to be understood that the foregoing isillustrative of the present invention and is not to be construed aslimited to the specific embodiments disclosed, and that modifications tothe disclosed embodiments, as well as other embodiments, are intended tobe included within the scope of the appended claims. The presentinvention is defined by the following claims, with equivalents of theclaims to be included therein.

1. A semiconductor device, comprising: an interlayer insulating layer ona substrate; plugs disposed in the interlayer insulating layer in afirst direction; interconnections which extend in a second directioncrossing the first direction and include a connection portion which hasa width smaller than a width of the first direction of the plugs and isin contact with the plugs, the interconnections having a same width asthe connection portion in the first direction; and a protection patternin which the connection portion penetrates, the protection pattern beinginterposed between the interlayer insulating layer and theinterconnections and extending on the interlayer insulating layer andthe plugs.
 2. The semiconductor device of claim 1, wherein the plugsinclude first plugs and second plugs, and wherein the first plugs andthe second plugs are disposed in the first direction, and each of thesecond plugs is disposed between the adjacent first plugs and is spacedapart from the first plugs in the second direction.
 3. The semiconductordevice of claim 1, wherein the connection portion has same width as topsurfaces of the plugs in the second direction.
 4. The semiconductordevice of claim 1, further comprising molding patterns between theinterconnections.
 5. The semiconductor device of claim 4, wherein themolding patterns which are in contact with side surfaces of theinterconnections extend in the second direction and are overlapped withedges of the plugs to be disposed on the protection pattern.
 6. Thesemiconductor device of claim 4, wherein the molding patterns includematerial having an etching selectivity with respect to the protectionlayer.
 7. The semiconductor device of claim 4, wherein the protectionpattern includes silicon nitride and the molding patterns includesilicon oxide.
 8. The semiconductor device of claim 1, furthercomprising a string selection line which is adjacent to the plugs on thesubstrate and extends in the first direction, word lines adjacent to thestring selection line and a ground selection line adjacent to the wordlines.